meowww :3
Remote
Nspace
@nspace@infosec.exchange
Eepy computer toucher. Likes to ride bikes. 31 years old. Formerly a CTF player. Dazed and confused, but trying to continue.
Meow
304
Followers
369
Following
16
Posts
Joined November 28, 2022
Languages:
it_IT, en_US, de_DE
Pronouns:
he/him
zoneinfo:
Europe/Zurich
Posts
Last week I cycled 840 km from Zürich to the Netherlands in 9 days. It was my first long bike trip and I brought way too many things but it was a lot of fun! I definitely want to do it again, maybe an even longer tour in the future 😊
I got very lucky with the weather (it never rained and it wasn't too warm) and took many pretty pictures. Enjoy!
Replying to
@eigenform@social.treehouse.systems
@eigenform@social.treehouse.systems oooo nice I think I saw them around 2015. It was a great show! I should go see them again
After nearly 20 years this album still owns so hard https://www.youtube.com/watch?v=YLXyvVCS6NU
So many epic riffs!
Replying to
@MarcAbrahams@mstdn.science
@MarcAbrahams
Oooo looks cool! What kind of volunteering is needed?
Replying to
@anthropy@mastodon.derg.nz
@anthropy@mastodon.derg.nz @chatcontrol@mastodon.social
You can see how each member of parliament voted https://howtheyvote.eu/votes/189574 https://howtheyvote.eu/votes/189270
Replying to
@anthropy__dup_5828@mastodon.derg.nz
@anthropy A lock sounds smart! I'm going to yolo it with 4 panniers and hopefully things don't get stolen 😅
Replying to
@anthropy@mastodon.derg.nz
@anthropy@mastodon.derg.nz that's a very square bike trailer, I'm used to them having more rounded corners haha
Replying to
@nytpu@tilde.zone
@nytpu@tilde.zone
Hmm I don't think this is it, DDR4 x4 chips have the same number of banks as x8 chips but twice as many rows for the same overall size. Why would anyone want that?
I don't think that using x4 chips gives you more banks: When DRAM chips are wired together in, say, a DIMM, the width of the data bus is fixed to something like 64 bits. By using x4 chips the designer has to wire 16 x4 chips in parallel instead of 8 x8 chips. All these chips are connected to the same address and control lines, so the same set of rows is open in all the chips at any given time. Using x4 chips lets you make the rank up to twice as big (in terms of bits stored overall) at the cost of having twice as many chips, but you could accomplish the same thing by having two ranks of x8 chips.
Why do DRAM chips come in different column widths (x4, x8, x16)? Why didn't we decide that, say, all chips must be x8? What are the use cases for different bit widths?
And why do we sometimes use x4 chips in PC/server DIMMs, when we have to array twice as many chips to reach a 64-bit word size compared to x8 chips? That seems counterintuitive, it means having twice as many chips on the DIMM and makes routing more complicated. 🤔
Does anyone know?
Replying to
@pixx@merveilles.town
Replying to
@gsuberland@chaos.social
@gsuberland @ryanc we have microcode for amd too :p and it works on the newest cpus unlike on intel. there are a lot of internal registes you can access only through microcode