Post #4050037
2026-07-24 00:29 UTC
@ldcd@social.treehouse.systems @whitequark@social.treehouse.systems @azonenberg@ioc.exchange there are none. all you get in there is checkboxes for what you want to init in FSBL or APP runtime contexts. for the FSBL (what I would expect to run from SRAM) all I've got enabled is DDR, GIC1 and RCC. under CORTEX_A7 the only option is to enable MMU and cache in APP, no other settings. FreeRTOS also only gets ticked in APP; no FSBL option there. all the other stuff like FMC, ETH1/ETH2, I2C1, SPI1, SPI2, USART1, RTC, TIM1, DTS, etc. are in APP.
Replies (3)
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@azonenberg@ioc.exchange 2026-07-24 00:30
@gsuberland@chaos.social @ldcd@social.treehouse.systems @whitequark@social.treehouse.systems yeah I don't think i can be of much help i just wrote my own FSBL from scratch and that image is my entire firmware
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@azonenberg@ioc.exchange 2026-07-24 00:44
@gsuberland@chaos.social @ldcd@social.treehouse.systems @whitequark@social.treehouse.systems and here i am doing pcie in my fsbl
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@ldcd@social.treehouse.systems 2026-07-24 00:43
@gsuberland@chaos.social @whitequark@social.treehouse.systems @azonenberg@ioc.exchange huh... do you get a freertos elf anywhere out of the build flow?