Post #3610156
2026-07-05 18:31 UTC
@0h00000000@ioc.exchange Also check clocks going into your SERDES and make sure they're proper frequencies/phases. I've had all manner of problems when my slow and fast domains weren't the right multiple or misaligned or something
Replies (1)
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@0h00000000@ioc.exchange 2026-07-05 18:49
@azonenberg@ioc.exchange Yeah, there is weirdness happening on a rotating basis and also during hsync events, no bueno for the clock. I was trying to use a single 4 lane LVDS bus instead of 4 single lanes to minimize all the rest logic and minimize skew.