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• Post #4402397

  I pulled the trigger on this camera board stack. Alif E8, OVT 8MP sensor, and 10/100 POE. 27.5mm diameter, and probably about 10 mm thick when assembled. I added some debug boards to the design too. I ordered 20 sets, but only 6 assembled, that way if there is a change we can order another batch of PCBs and if not, we can order the balance with PCBs already made.

• Post #4353162

• Post #4247256

  I heard/felt a loud thud earlier and wondered what it was. I went outside and saw a SUV had missed the curve in the road and hit our light pole and the neighbors fence. 3rd time in last 12 months.

• Post #4167887

  KiCad 9 crashed, so I'm taking this opportunity to install KiCad 10, which will be timely since it has upgraded differential pair tools that I will need later today.

• Post #4099630

  I was designing this 3 piece 27.5mm diameter camera board to be a rigid-flex PCB, but most PCB houses have trace/space limits of 4 mil on the rigid portion and limit blind vias to one layer deep, which causes challenges with BGAs. Also the 6L rigid flex stackups cause issues with 100 ohm differential traces being too wide. I think I'm going to look at just using very small board to board connectors. The Hirose DF40 20 pin looks promising. Any other recommendations? I'm looking for a boa...

• Post #4092208

  I just saw my first Stalink ad, and it was on Reuters.com (news site). It's also the first time I've seen them offer financing the hardware - $16/mo for 12 mos for the Mini. I think they want to juice the numbers for the upcoming quarterly results. I bet the next Starship launch will carry a load of the V3 satellites to a full orbit as well. This will be good timing to prop up share price since a bunch of lockups will be expiring at the same time.

• Post #4051244

  After the storm. Bye bye Bertha, the plants thank you for the rain.

• Post #4026104

  It was *really* hot in Houston today where the higher humidity usually moderates the temps a bit. The overnight *low* is going to be 85F!!! The state grid set a new all time record at over 90 GW. Not much wind, but solar was putting in 33 GW, and at dusk batteries peaked at 11.6 GW. That’s a lot of battery power! Wholesale prices were a low of $26/MWH when the batteries where charging and peaked at $349 right at 10PM.

• Post #3998468

  Baby FPGA! Lattice Crosslink NX, 72 ball WLCSP 3.7x4.1mm, 17kLUT, 4 lane hard MIPI.

• Post #3990384

  Has anyone had issues with putting a 10/100 Ethernet PHY too close to the magnetics? I have a super compact rigid flex design (27.75 mm diameter), and I'm cramming in the stuff pretty close. I'm maintaining a keep out directly under the magnetics, but the PHY IC body is 5mm away. An app note I read said keep it 25mm away.

• Post #3912570

  My office neighbor is throwing out an ancient PC. Compaq, circa 1999. Should I grab it and stick it in storage for an antique collection?

• Post #3833073

  I'm finally looking at flashing the FPGA from the MCU, and the 40k Lattice NX parts have a ~155k sized bitstream. So, when using I3C they can take it all in one chunk, or if breaking into multiple chunks, you cannot have a I3C stop condition until the very end. Well, my Alif MCU has a max I3C transaction size of 65k. The vendor driver does not expose a way to not end with a stop - and the methods I need are all declared static. So, I have to copy and paste their static methods into my own...

• Post #3814103

  Yay!!!!!!

• Post #3772439

  I mounted the LEDs on an aluminum heat spreader I had cut at Osh Cut and added a bolt on thermistor on the back side. When inside the stainless steel case, temps hit about 44C at 6 watts, or half power. The smaller cap looks much better, 82uF at 63V. The plan is to eventually use a PCB thermistor thermally coupled to the heat spreader with a spring terminal and a SMD part that themally conducts but is electrically isolated. I gotta test it out and probably tweak the fit some.

• Post #3719704

  I think I made these holes too big…

• Post #3717467

  It's obvious in hindsight, but cost $850 to learn... UNC vs UNF threads means coarse vs fine. I was under the impression that you had to specify threads per inch. Doh!

• Post #3707301

  DAC dimming is working. 12 watts of LED is pretty bright! I’m using heat sink for test since I haven’t coded the thermistor measurement and control loop yet.

• Post #3706578

  Blinky light, yay!

• Post #3705003

  Boards for the LED power supply arrived. Little board comically large cap. I for got to order the proper caps, 82uF at 63v, so I scrounged this guy up. He is part of the EMI filter and connnected through a couple ohms to damp any oscillations after filter inductor. I’ve got a pressure and humidity sensor in this board for feedback during submerged pressure testing.

• Post #3702908

  It's time to reboot my PC - 30 days was a good run. I closed everything and it's still 16GB of RAM used. (I reopened Chrome to post this)

• Post #3698684

  I just ordered a few ESD trays so I can swap out projects easily on the lab bench. Let's see how this ends up working in practice...

• Post #3618577

  Well crap, I don't have any monitors that can accept 1080p24, they all want a 60hz or better refresh rate. I'm limited to a 62.5Mhz pixel clock. It looks like 800x600 is the best I can do with what I have, and that will let me validate that my HDMI logic is working. The smaller BGA121 package would let me do 1500Mbps - or a 75Mhz pixel clock. I really need something with a SERDES interface(s), then I could just do display port over one lane. All those FPGAs need a paid version of the La...

• Post #3617788

  I wasn't getting signal out of the re-drivers, and I tried everything, for hours. And then I realized I had the I2C addresses swapped for the 2 redrivers, so I was talking to the one I wasn't using. Now I've got signal after the driver, but monitor isn't syncing up. I'm gonna try swapping some bits on the data lanes around like I had them originally.

• Post #3610103

  Well, there is a problem with the HDMI clock out from the FPGA - weird repeating pattern. I use a 4th LVDS DDR geared lane and stuff it with 1's or 0's on alternating 1/5 DDR clock signal. I might have my math wrong I'll need to double check here. Blue is 56MHz generated from SDR debug pin, and green is measured with diff probe on 560Mhz LVDS out. They should match.

• Post #3596897

  OMG - I FINALLY got the I2C to the HDMI re-drivers working. I took an hour off to go watch the fireworks and then came back and locked in. There were two main issues. First the MUX needed > 2.5v. Secondly, the EN pins had a 250k internal pull up, but when I measured them they were 0V. It turns out I tied them to extra FPGA pins in case I wanted to control them. The FPGA was uninitialized and pulling them down. Then I had one of the addresses wrong. But finally, the thing that should be UBER...

• Post #3590381

  Crap - I have a MUX for I2C for the HDMI drivers, and I routed 1V8 for VCC, but the datasheet says 2.5V minimum. It's a tiny package, but the rework is doable, the complicating factor is the million things I have hooked up to it for debugging.

• Post #3564318

  New stainless steel housings came in for the underwater LED light. Everything seems to fit, need to pressure test to confirm. PCBs for it come in next week. Design requirement is 50’ with rough service, but this guy is probably good to 1000’ submerged. 3mm thick body with 2mm thick sapphire window.

• Post #3547554

  It's looking like I have a valid HDMI signal going from the FPGA to the redriver IC. Next step is to get I2c to configure the driver which means going through the driver datasheet. I only have a 350Mhz scope, so I slowed the FPGA PLL down 8x from 525MHz so I could get a readable signal. There is some skew since I'm reading 10 bit word clock off a single ended debug pin (blue) and I'm using a 500MHz diff probe on the diff pair for the blue pixels (in green on scope) which contain the...

• Post #3476522

  Ok, well, second swing at this, HDMI in FPGA. This first pass used: assign aggregateDataClk = {rFlipped,gFlipped,bFlipped,clkFlipped}; And it produced interleaved data, which I didn't want, each color should stay on its own lane...

• Post #3449418

  Sunday morning Verilog debugging... I had added some parameters to a module to flip or complement a diff signal because I swapped polarity on the PCB to make routing easier. Hindsight is 20/20 - it wasn't my intention, but you can't put a not gate on the fast side of a DDR component. Doh! Problem corrected, and the code is now passing the Map phase.