Post #3565145
2026-07-03 20:08 UTC
@azonenberg@ioc.exchange I landed on a design with a separate descriptor file so I don’t have to put the data in ROM. Then a BSCANE2 exposes the capture RAMs over JTAG. Not configurable triggers or comparators yet….
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@azonenberg@ioc.exchange 2026-07-03 20:20
@craigjb@fosstodon.org My current debug model is ADIv5 esque, there's a bridge (currently only UART is implemented but it would be straightforward to add JTAG and more as transports) that connects an external-facing bus to a 32-bit APB bus inside the FPGA. You hook up an APB decoder/mux block and hang all of your debug IPs off that, you can also optionally have the same APB segment contain non-debug cores too. The bridge has a register you can query to get a pointer to a ROM table which has a list of addresses and types of all the other debug IPs allowing you to walk the whole chain from there on out.