Post #3565144
2026-07-03 20:20 UTC
@craigjb@fosstodon.org My current debug model is ADIv5 esque, there's a bridge (currently only UART is implemented but it would be straightforward to add JTAG and more as transports) that connects an external-facing bus to a 32-bit APB bus inside the FPGA.
You hook up an APB decoder/mux block and hang all of your debug IPs off that, you can also optionally have the same APB segment contain non-debug cores too.
The bridge has a register you can query to get a pointer to a ROM table which has a list of addresses and types of all the other debug IPs allowing you to walk the whole chain from there on out.
Replies (1)
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@azonenberg@ioc.exchange 2026-07-03 20:28
@craigjb@fosstodon.org I'm building the 8b10b ILA first, which is basically done and just needs some trigger stuff tweaked before I can call it finished. I already have a VIO. Next up will be a more generic ILA but I need to do some work on the scopehal data model to support multi bit vectors and think about the packing of probes into memory address space so it'll take a little longer to build out.