Post #2767885
2026-04-18 15:29 UTC
With a small bit of rework, the PHY solidly negotiates a gigabit connection. Unfortunately this shows that the rgmii bus traces aren't matched well enough for 125MHz ddr- the best clock delay I could find resulted in a 75% packet loss at 1000Mbps, but if i force the connection to 100Mbps then runs flawlessly.
That's all that is needed from this board rev, the goal was to verify basic functionality before spending time tuning things.
Replies (3)
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@cibomahto@social.v.st 2026-04-29 10:41
Produced a RevB of the board with nice squiggly lines, but the real issue turned out to be an excessive capacitor filter on the TX and RX clock lines. Removing that, even the RevA boards perform as expected.
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@cccpresser@chaos.social 2026-04-18 17:07
@cibomahto@social.v.st that bodge looks excellent.
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@23n27@dgc.social 2026-04-18 17:16
@cibomahto@social.v.st Thought it was just a diffpair swap at first but it's actually cursed