I'm investigating the original Berkeley RISC-I CPU out of historical interest and wonder why some instructions use more than one opcode (e.g. LDHI uses 16 opcodes 0x70...0x7F). I can't see why this is necessary – is this an optimization or am I missing something here?
Details seems to be provided in Corcoran, G.T., "Using ISPS to Specify the RISC I Architecture and Implementation," Master's Report, UCB (Dec. 1980), but I can't find this online.
#risc #berkeley #ucb #comparch #processor
