Post #4445120
2026-08-08 10:09 UTC
I'm investigating the original Berkeley RISC-I CPU out of historical interest and wonder why some instructions use more than one opcode (e.g. LDHI uses 16 opcodes 0x70...0x7F). I can't see why this is necessary – is this an optimization or am I missing something here?
Details seems to be provided in Corcoran, G.T., "Using ISPS to Specify the RISC I Architecture and Implementation," Master's Report, UCB (Dec. 1980), but I can't find this online.
#risc #berkeley #ucb #comparch #processor
Replies (1)
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@CyReVolt@mastodon.social 2026-08-08 10:25
@me_@sueden.social It looks to me like a tweak to look at less of the bits when decoding for very common instructions (maybe they did some profiling). The AND, XOR and OR are similar; you only need to look at some more significant bits and already know there is no other instruction possible when those bits are set.