Post #4445117

@CyReVolt@mastodon.social That would make sense, but instruction decoding seems to use a PLA in the RISC-I instead of a net of combinational logic gates (see p. 6 of [1]). Using redundant opcode encodings would then not result in a reduction of chips space, I think. [1] https://www2.eecs.berkeley.edu/Pubs/TechRpts/1983/Archive/CSD-83-135.pdf