Post #4350100
2026-08-03 09:00 UTC
@azonenberg@ioc.exchange Have some clock line with signal integrity poor enough that the ringing causes infrequent extraneous clock cycles and short-pulse glitches.
Replies (1)
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@azonenberg@ioc.exchange 2026-08-03 09:05
@anymouse_404@glitch.social That seems tricky to consistently, reliably create, any ideas on how? I'm mostly looking to have some lines I can put probes across and e.g. show how probe loading affects step response etc, plus a bunch of protocol data.