Post #4350099
2026-08-03 09:05 UTC
@anymouse_404@glitch.social That seems tricky to consistently, reliably create, any ideas on how?
I'm mostly looking to have some lines I can put probes across and e.g. show how probe loading affects step response etc, plus a bunch of protocol data.
Replies (1)
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@azonenberg@ioc.exchange 2026-08-03 09:09
@anymouse_404@glitch.social creating reproducible SI issues is similar to the problem of creating reproducible soldering defects on the reworkctf - it's easy to turn 99.999% yield to 95% yield even by accident. It's a lot harder to get a consistent 0% yield lol