Post #4252814
2026-07-30 20:42 UTC
So basically we're looking at a 7mm square MCU paired with a 9mm square FPGA.
Assuming we use the full 37 FMC pins between the two, the MCU will have 75 free IOs and the FPGA will have 36. Not a ludicrous number, but if we're focusing on a high density low pin count option that doesn't seem unreasonable.
But I definitely want to feel out the design space more before committing to anything.
Replies (1)
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@azonenberg@ioc.exchange 2026-07-30 20:45
In particular, for another 3mm on a side, I can bump the FPGA up to the T120F324 with 112K LEs, 130 GPIOs (93 free after FMC) and get 5.4 Mbit of BRAM, 320 multipliers, and 7 PLLs plus even a hard DDR3/LPDDR3 controller assuming you can actually find said RAM in 2026. That seems like a much more capable pairing than the T20.