Post #4252813
2026-07-30 20:45 UTC
In particular, for another 3mm on a side, I can bump the FPGA up to the T120F324 with 112K LEs, 130 GPIOs (93 free after FMC) and get 5.4 Mbit of BRAM, 320 multipliers, and 7 PLLs plus even a hard DDR3/LPDDR3 controller assuming you can actually find said RAM in 2026.
That seems like a much more capable pairing than the T20.
Replies (1)
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@azonenberg@ioc.exchange 2026-07-30 20:49
If we allow 1mm clearance between the components and 1mm on the perimeter, as a floor on overall SoM size, we'd be looking at 14mm x 21mm in this scenario, although there will probably need to be some voltage regulators and SPI flashes and passives so I'm not yet sure how small I could actually pack it. Assuming 13 x 20mm ball field, with an 0.8mm ball pitch that gives roughly 16 x 25 = 400 ball sites available for connecting to the host board which should be sufficient. Still a lot of open questions, one of the biggest being if we can figure out how to do ball attach on my friends' PnP in a cost effective / scalable manner because tweezering hundreds of balls is not happening