Post #4252651
2026-07-30 20:39 UTC
Once it becomes available the TI125 (8mm, 36 HVIO, 110 HSIO, no transceivers) will be an extremely attractive option for this type of project.
But for now it seems like the T20F169 is a clear winner - a third of the price of the competing Xilinx part and only 1mm larger on a side.
The T20 has 1.04 Mb of block RAM, 36 multipliers, and 5 PLLs.
The 7S15 has 360 Kb of BRAM, 20 DSPs, and 4 PLLs.
So unless you need the speed of the 28nm Xilinx fabric over the 40nm Efinix fabric, the Trion is the way to go. For MCU peripheral expansion it seems a good option.
Replies (1)
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@azonenberg@ioc.exchange 2026-07-30 20:42
So basically we're looking at a 7mm square MCU paired with a 9mm square FPGA. Assuming we use the full 37 FMC pins between the two, the MCU will have 75 free IOs and the FPGA will have 36. Not a ludicrous number, but if we're focusing on a high density low pin count option that doesn't seem unreasonable. But I definitely want to feel out the design space more before committing to anything.