Post #4021430
2026-07-22 22:07 UTC
I2C specifies a fall time of 12 to 300 ns at 3.3 V, rise time of 20 to 300 ns in fast mode, no minimum rise time in standard mode.
Any idea why the minimum rise/fall times? I'd need extra resistors and caps to make an FPGA go that slow. Slow slew minimum drive is still sub-nanosecond.
Replies (1)
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@0h00000000@ioc.exchange 2026-07-22 22:59
@dlharmon@chaos.social I know that I3C can coexist with I2C because I2C is supposed to have 50ns glitch filters and won't see the extra fast 10-20mbps traffic on the bus.