Post #3892701
2026-07-17 10:15 UTC
@MarkAtMicrochip@mastodon.social I mean, the fully loaded up version is too much, fair! but then what about RV32I?
AFAIK no virtual memory, no supervisor mode, no complex memory management, and it's more basic than ARM in some ways (e.g Load/Store, orthogonal registers, but without ARM's condition flags on every instruction).
And AVR has a fragmented memory map (Data SRAM, Program Flash, EEPROM) requiring special instructions (LPM/SPM), whereas RISC-V uses a flat, uniform 32-bit memory map. Just my two cents
Replies (1)
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@MarkAtMicrochip@mastodon.social 2026-07-17 18:59
@anthropy@mastodon.derg.nz I think your right, although AVR gives me the opportunity to explain and demonstrate Harvard architecture. I just don’t have a good RV32 board. Maybe in an FPGA, but that presents its own set of issues