Post #3547554

It's looking like I have a valid HDMI signal going from the FPGA to the redriver IC. Next step is to get I2c to configure the driver which means going through the driver datasheet. I only have a 350Mhz scope, so I slowed the FPGA PLL down 8x from 525MHz so I could get a readable signal. There is some skew since I'm reading 10 bit word clock off a single ended debug pin (blue) and I'm using a 500MHz diff probe on the diff pair for the blue pixels (in green on scope) which contain the vsync and hsync code words during those events. Purple is hsync from a debug pin and yellow is vsync from a debug pin. This is at 1080p24 divided by 8 for testing. You can see a zoomed out view at the top of the scope image.