Post #3476522
2026-06-29 19:54 UTC
Ok, well, second swing at this, HDMI in FPGA.
This first pass used:
assign aggregateDataClk = {rFlipped,gFlipped,bFlipped,clkFlipped};
And it produced interleaved data, which I didn't want, each color should stay on its own lane...
Replies (1)
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@0h00000000@ioc.exchange 2026-06-29 19:57
So then I tried interleaving the data when assigning.. I could use primitives directly, but Lattice strongly urges me not to. So: assign aggregateDataClk[0] = rFlipped[0]; assign aggregateDataClk[4] = rFlipped[1]; assign aggregateDataClk[8] = rFlipped[2]; assign aggregateDataClk[12] = rFlipped[3]; assign aggregateDataClk[16] = rFlipped[4]; etc... Yields something that looks correct: