@PierreLebeaupin@mastodon.gougere.fr
Post #3062336
2026-04-14 21:53 UTC
Indeed, it was the intent for RISC-V code to use very short branches when other architectures would have used their conditional move/select instructions, but this obviously can’t be a solution for constant-time code sequences.
Some ISAs are apparently considering “constant-time” variants of some their instructions to better support this use case, but can this be applied here?
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@PierreLebeaupin@mastodon.gougere.fr 2026-04-14 21:53
The very notion of a “constant-time branch” seems iffy: a whole new RISC-V instruction with specific scheduler treatment, and very little expressivity as it wouldn’t encode backwards jumps (obviously) and probably not jumps to beyond a dozen bytes either. So might this new requirement of supporting constant-time code finally cause RISC-V to add a conditional select instruction as part of the base ISA (or an official extension)? That would seem the most likely outcome.