Post #2938337
2026-05-02 11:43 UTC
It would be easier to use one clock domain for the whole Isle design, but that forces everything (CPU, graphics, audio et al) to run at the pixel clock. Instead, I run the system at one clock, and the display logic is free to run at the pixel clock. The price is handling CDC in the display device.
Replies (1)
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@WillFlux@mastodon.social 2026-05-05 19:28
The TMDS clock wasn't meeting timing on #ULX3S. There is so little logic in the clk_pix_5x domain I doubted I could do much. Then I realised each channel shared a small critical ring counter. Giving each colour channel its own added 100 MHz+ to the max frequency! #FPGA 🚀 https://github.com/projf/isle/blob/main/hardware/arch/ecp5/dvi_generator.v