Post #2938338

The TMDS clock wasn't meeting timing on #ULX3S. There is so little logic in the clk_pix_5x domain I doubted I could do much. Then I realised each channel shared a small critical ring counter. Giving each colour channel its own added 100 MHz+ to the max frequency! #FPGA 🚀 https://github.com/projf/isle/blob/main/hardware/arch/ecp5/dvi_generator.v