Post #2857973
2026-05-15 12:47 UTC
my upcoming FPGA dev board "#bare_metal".
most tests are done, most changes and bugfixes are in this V2. not sure when I got time for a "tapeout" ;)
- 16x8 SPI based RGB LED display
- single PMOD interface
- OK button and D-pad
- USB bootloader
- 3 user bitstreams by default, extendable to dozens
- LiPo battery with protection and management
- comes with a PCB stand
- PCB stand comes with pinout tables
#FPGA #bare_metal #yosys #nextpnr #verilog #amaranth #spade #HDL #nametag
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