Post #2773655
2026-04-20 18:21 UTC
@cmb@cathode.church ok I grabbed the laptop and it's unchanged from the PDF
I don't understand how this⇒ "During reset, DIR pins from the FPGA are high, to prevent all-high outputs in that case, A and B are swapped compared to revC." can be possible at all? Either I'm having a very 🤪 moment or it's seriously fishy.
Replies (1)
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@cmb@cathode.church 2026-04-20 19:41
@equinox@chaos.social oh yeah, good catch, i definitely either mirrored the supplies once too often or once too few. thanks 😬 gonna update it real quick and push the fixed schematic.