Post #2272346
2026-05-04 23:40 UTC
@resistor@mastodon.online @whitequark@social.treehouse.systems @penguin42@mastodon.org.uk WTF???
Replies (2)
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@whitequark@social.treehouse.systems 2026-05-04 23:43
@regehr@mastodon.social @resistor@mastodon.online @penguin42@mastodon.org.uk i'm so glad it's not just me haha
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@resistor@mastodon.online 2026-05-04 23:43
@regehr@mastodon.social @whitequark@social.treehouse.systems @penguin42@mastodon.org.uk `vmul.f64 d3, d3, d10` The D-registers are the low 64-bits of each vector register. So this operation does an f64 fmul on quantities that are only 64-bits wide, and writes then to the low 64-bits of the register, implicitly zero-filling the high part if it exists (which it presumably doesn't on a core that only implements VFP and not NEON).