Post #2301190
2026-05-04 23:43 UTC
@regehr@mastodon.social @whitequark@social.treehouse.systems @penguin42@mastodon.org.uk
`vmul.f64 d3, d3, d10`
The D-registers are the low 64-bits of each vector register. So this operation does an f64 fmul on quantities that are only 64-bits wide, and writes then to the low 64-bits of the register, implicitly zero-filling the high part if it exists (which it presumably doesn't on a core that only implements VFP and not NEON).
Replies (2)
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@regehr@mastodon.social 2026-05-04 23:44
@resistor@mastodon.online @whitequark@social.treehouse.systems @penguin42@mastodon.org.uk got it... thanks!
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@resistor@mastodon.online 2026-05-04 23:49
@regehr@mastodon.social @whitequark@social.treehouse.systems @penguin42@mastodon.org.uk Other tips for anyone wanting to learn to read it: - Destinations are the first operand, except for stores - Square-bracketed expressions are indexed addressing modes. - I think most of the opcodes are self-explanatory if you just ignore the V-prefix. VMLS is multiply-subtract: DEST -= RA * RB