@whitequark@social.treehouse.systems
Post #2272318
2026-05-04 23:16 UTC
@regehr@mastodon.social @penguin42@mastodon.org.uk yep! it has a little state machine which can read out the bitstream from the flash. it has like a half dozen ways you can program it but the basic idea is that the FPGA has internal SRAM with a very custom structure organized in frames, and you have several ports through which these frames can be loaded (JTAG, SPI initiator, SPI peripheral, internal reconfiguration port, some others)
at power up the SRAM has nothing inside and it has to be loaded somehow
Replies (2)
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@regehr@mastodon.social 2026-05-04 23:17
@whitequark@social.treehouse.systems @penguin42@mastodon.org.uk got it I somehow thought that these things held program persistently
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@penguin42@mastodon.org.uk 2026-05-04 23:17
@whitequark@social.treehouse.systems @regehr@mastodon.social It's pretty common for this to be loaded from a CPU that comes up first; I worked with some one long ago doing that.