Post #2178000
2026-04-17 22:29 UTC
@CanLehmann@mastodon.social @verijit@mastodon.social @cfbolz@mastodon.social Your speedup is rather more impressive than ours :)
Replies (1)
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@CanLehmann@mastodon.social 2026-04-17 22:33
@ltratt@mastodon.social @verijit@mastodon.social @cfbolz@mastodon.social I think this can be to some extent attributed to how Verilog designs work from an architectural perspective. I don't know the exact numbers right now, but I think we are able to remove >99% of instructions (exact numbers depend on the core anyways, but my point is that the difference is absolutely insane). We also wrote a custom meta-tracer specifically targeted at the problem (https://github.com/can-lehmann/metajit.cpp)