Post #2178001
2026-04-17 22:33 UTC
@ltratt@mastodon.social @verijit@mastodon.social @cfbolz@mastodon.social I think this can be to some extent attributed to how Verilog designs work from an architectural perspective. I don't know the exact numbers right now, but I think we are able to remove >99% of instructions (exact numbers depend on the core anyways, but my point is that the difference is absolutely insane). We also wrote a custom meta-tracer specifically targeted at the problem (https://github.com/can-lehmann/metajit.cpp)
Replies (2)
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@ltratt@mastodon.social 2026-04-17 22:38
@CanLehmann@mastodon.social @verijit@mastodon.social @cfbolz@mastodon.social I've been pitching meta-tracing for CPU simulators for almost exactly 10 years, so I'm convinced :)
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@smarr@mastodon.acm.org 2026-04-18 10:14
@CanLehmann@mastodon.social @ltratt@mastodon.social @verijit@mastodon.social @cfbolz@mastodon.social oh, so, this is not based on RPython? Fun stuff! CF, might you be talking about it at ICOOOLPS? https://2026.ecoop.org/home/ICOOOLPS-2026