Post #1647241

2026-04-03 16:32 UTC

My first thought was that it could be a problem with the Pico 2, either with the code or the RP2350 A2 stepping chip. So, a couple of days before, I built a second #PsiDrive and put in a Pico 1. But the fault remained with with Pico 1. This meant it was an issue with my code somewhere. I thought it was strange that I'd never noticed it before, so it must be some weird edge case.

Replies (1)

@thelastpsion@oldbytes.space 2026-04-03 16:39

#Psion SSDs are basically made up of a single #ASIC and between one and eight storage chips. These chips could be ROM, battery-backed DRAM, battery-backed PS-RAM, or two different types of flash. Psion used two different custom ASICs for their SSDs. The earliest ones use ASIC5, the later ones ASIC4. Why 5 then 4? From what I gather, ASIC4 and ASIC5 were planned at roughly the same time, but ASIC4 went through a few changes before production, so was delayed. ASIC4 was originally meant to be a cut-down ASIC5 with just the storage parts remaining - things like the RS232 interface were removed. However, as time went on, ASIC4 had a few features added. It kept compatibility with ASIC5's storage mode, but added some more ASIC4-specific modes for use with peripherals. I actually have two Psion Games 2 SSDs - one with ASIC4 and one with ASIC5. This is great for testing. However, these ROM SSDs didn't show up the edge case that cause this fault, as we shall see.

Open ##1647242