Post #1647242

2026-04-03 16:39 UTC

#Psion SSDs are basically made up of a single #ASIC and between one and eight storage chips. These chips could be ROM, battery-backed DRAM, battery-backed PS-RAM, or two different types of flash. Psion used two different custom ASICs for their SSDs. The earliest ones use ASIC5, the later ones ASIC4. Why 5 then 4? From what I gather, ASIC4 and ASIC5 were planned at roughly the same time, but ASIC4 went through a few changes before production, so was delayed. ASIC4 was originally meant to be a cut-down ASIC5 with just the storage parts remaining - things like the RS232 interface were removed. However, as time went on, ASIC4 had a few features added. It kept compatibility with ASIC5's storage mode, but added some more ASIC4-specific modes for use with peripherals. I actually have two Psion Games 2 SSDs - one with ASIC4 and one with ASIC5. This is great for testing. However, these ROM SSDs didn't show up the edge case that cause this fault, as we shall see.

Replies (1)

@thelastpsion@oldbytes.space 2026-04-03 17:06

A quick side note: The #Psion SIBO Serial Protocol (SIBO-SP) is a proprietary two-wire serial protocol, a bit like I2C with CLK and DATA lines, and the concept of master and slave devices. (From memory, the term "master" is never used in the HDK, but "slave" is.) To talk to a slave, the master sends a control frame with an selection ID. For this discussion, all you need to know is ID:2 is ASIC5 and ID:6 is ASIC4. So, the SIBO-SP control frame "Select ID:6" means, "Hello, are you an ASIC4?" If yes, the response will be a byte with information about how ASIC4 is set up. If no, the response will be 0x00. (Side-side note: ID:2 is specifically ASIC5 in storage mode. ASIC5 also uses ID:3 for peripherals such as RS232 comms.)

Open ##1647243