@PierreLebeaupin@mastodon.gougere.fr
Post #1184721
2026-04-14 21:53 UTC
Rereading Andrew Waterman’s PhD dissertation, on how RISC-V learned from the limitations and missteps of its ISA predecessors — MIPS, SPARC, and ARM of course (and also x86), but Alpha and OpenRISC too — it’s remarkable how well it holds up, 10 years later: for instance, the inclusion of both the lr/sc pair and individual atomic memory operations (that scale better under contention) matches our still increasing SMP (with P & E cores)
https://people.eecs.berkeley.edu/~krste/papers/EECS-2016-1.pdf
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@PierreLebeaupin@mastodon.gougere.fr 2026-04-14 21:53
The same way, the provision for ISA extensions for tightly coupled but also less tightly coupled coprocessors does have renewed significance with the onset of chiplets; and the considerations on making sure the omitted features do not burden the microarchitecture with too much state are very welcome post Meltdown and Spectre, which have shown we would be better off with much less of that state, by making it architecturally explicit and/or reducing our need for it. However…