Post #3062333

2026-04-14 21:53 UTC

The same way, the provision for ISA extensions for tightly coupled but also less tightly coupled coprocessors does have renewed significance with the onset of chiplets; and the considerations on making sure the omitted features do not burden the microarchitecture with too much state are very welcome post Meltdown and Spectre, which have shown we would be better off with much less of that state, by making it architecturally explicit and/or reducing our need for it. However…

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@PierreLebeaupin@mastodon.gougere.fr 2026-04-14 21:53

However, what has occurred in the last 10 years is that not only computation latency side channel leaks needed to be plugged, but that this couldn’t reasonably be done by second-guessing the compiler and processor: “constant-time computation” patches have recently been written to ensure, when needed, the compiler emits straightline code, so that whether any instruction is executed or not does not depend on the input data, and all are constant time https://github.com/llvm/llvm-project/pull/166702

Open ##3062334