Post #810511
2026-03-27 18:05 UTC
SystemLisp - an HDL simulator written in Common Lisp
https://github.com/systemlisp
#lisp #commonlisp #hdl #rtl #verilog #design #verification #vhdl #systemverilog #vlsi #programming #fpga
Replies (1)
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@amoroso@oldbytes.space 2026-03-27 20:18
@jackdaniel@functional.cafe may be interested in this as it also runs on ECL. @graybeard85@universeodon.com