2026-09-21 18:15 UTC
@jaseg@chaos.social @gsuberland@chaos.social @azonenberg@ioc.exchange @aleksorsist@mastodon.social reminded me of this hack from 10 years ago: https://hackaday.com/2016/03/15/sdram-logic-analyzer-uses-an-avr-and-a-dirty-trick/
Wonder if it might be possible to do something similar with a high speed ADC and DDR5 DRAM?
Replies (1)
-
@azonenberg@ioc.exchange 2026-09-21 18:17
@RoganDawes@infosec.exchange @jaseg@chaos.social @gsuberland@chaos.social @aleksorsist@mastodon.social not easily since DDR has a whole command protocol you have to send and row/column addresses taking turns on the C/A bus. You might be able to do it with like a QDR-II+ SRAM. But not a modern DRAM.