Post #4087385

Replies (1)

• @charlotte@akko.chir.rs 2026-07-25 12:25

  alignment matters because outside of x86: misaligned memory access are slower (sometimes only 2-3x, sometimes requiring taking a trap into the kernel which emulates the read)may not be atomic where aligned access would bemay not be available as atomic accesses at all nvm there are x86 instructions that require strict alignment (simd instructions) big endian has issues now because everything is written exclusively for little endian systems x86’s memory ordering is total store order, meaning that writes have identical order between cores and hardware threads. that does mean that a lot of instructions are already atomic, but at the same time the relative order of stores between threads is unspecified? just that they are consistent. Other ISAs have way weaker requirements (requiring explicit barriers to make sure that reads and writes can’t cross the instruction). in a way x86 has a read fence before stores and a read-write fence after stores

  Open ##4087505