Post #3765611
2026-07-11 21:21 UTC
CPU architecture in which each register is extended with the standard set of arithmetic-result flags (zero, negative, carry, etc), which are set by anything that writes that register; conditional instructions can read these flags from any register; thus splitting the difference between "one flags register" and "predicate bits" architectures
Replies (1)
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@david_chisnall@infosec.exchange 2026-07-12 17:00
@zwol@masto.hackers.town I almost like this, but if registers are not the size of memory words then context switching is painful (though rare). More importantly, stack spills are annoying. You might be able to get around this with an ABI that makes only the non-flags bits of a register callee-save so you must explicitly move flags to the low bits or the stack if you want to preserve them across calls.