Post #3568887

IMEC has laid out its roadmap towards a 0.3nm process in 2038. https://www.tomshardware.com/tech-industry/semiconduct... The article notes that this is marketing nonsense - well, the part you can read doesn't, but it's there in the details that you can't read - with actual feature sizes in the 10-20nm range. Since a single silicon atom has a diameter of 0.2nm, you can rest assured they're not building circuits that size. The 0.3nm instead refers to the effective density thanks to increased use of 3D production to stack transistors vertically.