Post #3213147

@ids1024@fosstodon.org @jernej__s@infosec.exchange @atax1a@infosec.exchange @thephd@pony.social as a rule, CISCs did not conform their ISAs to the microarchitecture. That was a bigger thing with RISC, having the ISA and microarchitecture have a close fit. But honestly, that was and still is a bad idea. ISAs shouldn't fit the HW. They should fit being easy to use to get good performance. The old RISC ISAs became road blocks whenever new microarchitectural innovations were made. No good way to make multiplication hardware? Just do it in software, CISCs all microcode it anyway. Someone invents really good HW multiplication? CISC users just upgrade and multiplication becomes faster, RISC users need to update their compilers, and make new binaries that won't run on the previous generation. Microarch induces delays in some situations? Aha, let's have delay slots! New microarchitectural paradigm makes delay slots super annoying? Shoot.