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@nytpu@tilde.zone
Post #2968704
2026-02-18 00:28 UTC
@nspace@infosec.exchange Into the weeds of how SDRAM works, but I think the smaller widths are the same exact same sets of cells, just wired into columns/rows/banks differently. Lower column widths have more banks (because the lower bit width means more columns total, but the number of columns per row and rows per bank remains the same, so there's more overall banks).
More banks per chip is actually somewhat desirable because different banks can have accesses interleaved between each other, but you can only access one row of a given bank at once. So a clever SDRAM controller could access twice the number of addresses at once with an x4 chip as an x8 chip, and twice the number of addresses at once with an x8 chip than an x16 chip. ("at once" meaning not incurring the delays required to close one row and open another)
But of course it comes with the cost of needing twice the number of chips to fulfill the necessary data bus width with one access
(n.b. this is with my shaky knowledge of how SDRAM works, I'm not an expert lol)
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@nytpu@tilde.zone
Hmm I don't think this is it, DDR4 x4 chips have the same number of banks as x8 chips but twice as many rows for the same overall size. Why would anyone want that?
I don't think that using x4 chips gives you more banks: When DRAM chips are wired together in, say, a DIMM, the width of the data bus is fixed to something like 64 bits. By using x4 chips the designer has to wire 16 x4 chips in parallel instead of 8 x8 chips. All these chips are connected to the same address and control lines, so the same set of rows is open in all the chips at any given time. Using x4 chips lets you make the rank up to twice as big (in terms of bits stored overall) at the cost of having twice as many chips, but you could accomplish the same thing by having two ranks of x8 chips.
Open ##2968705