Post #2849077

Right, let's do this properly. Apparently these programmable logic devices prefer clock enable signals that are high only for the duration of a master clock cycle, because power, synchronisation, ease of synthesis etc. That's why I kept seeing that design pattern in all the other retro computer Verilog projects I've been studying. So here we are with the beginnings of my own custom video display generator, creating all the clock signals for driving the CPU and system bus, as well as the 2, 3, 4, 6 or 8 pixels per byte I want for my video shifter.