Post #2409964

2025-09-09 05:29 UTC

@JamesWidman@mastodon.social @steve@discuss.systems @regehr@mastodon.social You can see the trajectory with Intel's E-cores. They went 3-wide fetch/decode in Goldmont+ (2017) to constrained 2x 3-wide in Tremont (2020) to much more flexible 2x 3-wide in Gracemont (2021) to 3x 3-wide in Skymont (2024). Over the same period, they widened the backend from 7-wide (Goldmont) to 10-wide (Tremont) to 17-wide (Gracemont) to 26-wide (Skymont). So just way more focused on perf via higher IPC instead of clock. (Because it's more power-efficient.)

Replies (1)

@rygorous@mastodon.gamedev.place 2025-09-09 05:37

@JamesWidman@mastodon.social @steve@discuss.systems @regehr@mastodon.social Now wide decode specifically (backend less so, that's neither here nor there) is actually appreciably easier for ARM AArch64 because it's fixed-width 32-bit instructions. That was something that I was actually wondering whether it might screw over x86 one day. But Tremont and later with their clustered decode approach (that is, getting 6 or 9 insns/cycle by doing, essentially, out-of-order decode using 2 or 3 separate 3-wide decoders) are a game changer.

Open ##2409965