@GDCPresoReviews@mastodon.gamedev.place
2026-03-21 21:23 UTC
So, if you're going to hit memory, you'll want to manually schedule either a) expensive instructions, or b) other memory operations, concurrently, to maximize parallelism of the chip. So interesting!!!
The previous diagram also lists the number of unnamed registers, which is less than I expected (72 and 64); I expected there would be hundreds. Interesting!
Another really interesting part: it turns out that interacting with the cache is done in transactions.
4/6
Replies (2)
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@GDCPresoReviews@mastodon.gamedev.place 2026-03-21 21:27
Each cycle can only issue a single one of these cache transactions. This is why cached SIMD loads are faster than cached scalar loads: the bottleneck isn't actually the throughput of the cache, but is instead the setup time of the cache transactions. You get 4x more data out of the cache per cycle than you would if you issued scalar loads. Wild!!! The rest of the presentation was working through examples of some common algorithms on some common data structures. 5/6
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@zeux@mastodon.gamedev.place 2026-03-21 21:25
@GDCPresoReviews@mastodon.gamedev.place Jaguar is a tiny and very slow core by modern standards. "hundreds" is correct for modern cores, e.g. here's Zen 4 diagram.