Post #2177996
2026-04-22 16:51 UTC
@cfbolz@mastodon.social Ah OK, I've just read them; yeh I can see how that's easier for language JITing rather than CPU; for CPU emulation it's often possible to share a lot between the interpreter and JIT-IR creation.
So hmm, for meta-tracing of your verilog case, is this just the RISC-V core that you're treating and meta tracing it's PC and branches?
Replies (1)
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@cfbolz@mastodon.social 2026-04-22 17:25
@penguin42@mastodon.org.uk yes, we meta trace the core. It's generic, so it works for other cores too (but we haven't tried that for a super wide variety of cores yet)