Post #2177991
2026-04-17 20:49 UTC
@penguin42@mastodon.org.uk @CanLehmann@mastodon.social @verijit@mastodon.social it's 'meta' because the tracing jit is parametrized by the core. You can trace a riscv program according to the Verilog code of hazard3, or some other riscv core (or do the same thing for another isa and corresponding core entirely). The jit infrastructure is shared for all these cases
Replies (2)
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@cfbolz@mastodon.social 2026-04-17 20:57
@penguin42@mastodon.org.uk @CanLehmann@mastodon.social @verijit@mastodon.social does that make any sense? Happy to answer more questions about it!
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@penguin42@mastodon.org.uk 2026-04-17 22:02
@cfbolz@mastodon.social Thanks.