Post #2161248

@tom_verbeure @verijit @cfbolz It currently requires a small bit of annotation in the form of an external JSON file. While writing these annotations is very manageable in my opinion, we are investigating a couple of options to automate the annotation process. The Verilog itself does not have to be modified at all. You just place it into a testbench and then simulate it. Our simulator does a whole bunch of optimizations and the just in time compilation automatically.