Post #1430559

2026-04-17 19:56 UTC

We&#39;ve released a demo of the project @CanLehmann and I have been working on: @verijit is a meta-tracing Verilog emulator that specializes the simulated core to the machine code that is being executed on top of it. Was lots of fun to work on! I&#39;m quite happy with the results too, we reach two orders of magnitude improvement over Verilator for a simple RISC-V core https://www.youtube.com/watch?v=PXgUsEjvAOY

Replies (4)

@cfbolz@mastodon.social 2026-04-17 21:20

It's very amusing to me that there were two different new meta tracing jits announced this week, yk by @ltratt@mastodon.social and @verijit@mastodon.social And both are using a Mandelbrot demo! @CanLehmann@mastodon.social

Open ##2177987
@penguin42@mastodon.org.uk 2026-04-17 20:34

@cfbolz@mastodon.social @CanLehmann@mastodon.social @verijit@mastodon.social What do you mean by 'meta tracing' - you say specialising the core; by core do you mean you're working at the instruction level of the emulated hazard rather than at the verilog level?

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@krono@toot.berlin 2026-04-17 22:11

@cfbolz@mastodon.social @CanLehmann@mastodon.social @verijit@mastodon.social \ o /

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@lindsey@recurse.social 2026-04-18 14:09

@cfbolz@mastodon.social @CanLehmann@mastodon.social @verijit@mastodon.social This is so cool! > specializes the simulated core to the machine code that is being executed on top of it Is this like a first-Futamura-projection sort of thing?

Open ##2178011