Post #1341977
2026-04-17 19:48 UTC
I can finally talk about what I did during the last year! In collaboration with @cfbolz we developed a Verilog simulator called verijit based on meta-tracing just in time compilers. The results are pretty crazy: verijit is up to 100x faster than verilator for simulating processors.
You can follow us on Mastodon @verijit
We have a neat mandelbrot demo below:
https://www.youtube.com/watch?v=PXgUsEjvAOY
#fpga #verilog
Replies (3)
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@mtnrbq65@social.vivaldi.net 2026-04-17 22:21
@CanLehmann @cfbolz @verijit That is an insane speedup! Kudos!
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@tom_verbeure@mastodon.social 2026-04-18 04:04
@CanLehmann @cfbolz @verijit The project page says “Verilog processor simulations”. Does this mean that it is not a generic Verilog simulator?
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@thezoq2@mastodon.social 2026-04-18 07:15
@CanLehmann @cfbolz @verijit That's extremely cool! Any chance it'll be open source?