@Aissen@social.treehouse.systems
Post #1333849
2026-03-27 12:12 UTC
Simon shows how some simple RISC-V instructions are designed, and how he then build a CPU core in the NAND simulator. The memory was not simulated though, only the CPU core.
#RustInParis
Replies (1)
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@Aissen@social.treehouse.systems 2026-03-27 12:12
For devices, they are "memory-mapped"; there's a device to exit the simulation and a serial port. He planned to do a pixel buffer, but it's quite slow. #RustInParis